The traditional byte-erasable EEPROM based on floating gate tunnel oxide (FLOTOX) technology has many significant drawbacks. First, the cell size is very large. Second, the floating gate requires many process steps to manufacture. Third, the operating voltage (e.g., 15V) is very high and causes the cell to have a very long channel length. Additionally, extra process steps are needed to form high voltage devices to generate the high operating voltage. Fourth, the technology is not logic-process based. It may require 7-9 extra mask layers over the logic process, which significantly increases the final chip cost for embedded memory applications.
Recently, another non-volatile memory technology based on using a charge-trapping layer, such as SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) has becomes popular due to its advantages of cheaper process and logic-compatibility. Compared with the floating gate technology, the SONOS technology only requires 2-3 extra masks over the logic process and can be integrated into the standard logic process easily. This significantly reduces the chip's manufacturing cost. Therefore, SONOS is more attractive than floating gate especially in embedded memory applications.
However, typical SONOS cells are used only in flash memory (also called flash EEPROM), not EEPROM (also called ‘byte-erasable’ EEPROM). The flash memory erases the cells in a large block or sector size, and therefore is suitable only for storing system programs. When storing data, even one data item, flash memory operates on the entire data block, which is very slow. Therefore, flash memory may not be suitable for data storage.
For applications that require data-intensive operations, such as SIM cards, bank cards, and security cards, the data needs to be stored in ‘byte-erasable’ EEPROM. In this type of EEPROM, the selected byte's data is erased and then programmed with the new data. This operation requires a mechanism to prevent data errors in unselected cells due to “erase-disturb” or “program-disturb” when erasing or programming selected cells.
The memory cells of byte-erasable EEPROM are connected with word lines (WL) and bit lines (BL). During erase and program operations when high voltages are applied to the WL and BL of selected cells, the voltages may also affect unselected cells that share the same WL and BL. To prevent the unselected cells from being erased or programmed, ‘inhibit’ voltages are applied to the unselected WL and BL to reduce the unselected cells' electrical field, and thus prevent the unselected cells from being erased or programmed. However, even though inhibit voltages are applied, the unselected cells' data may gradually change over time as more read and program operations are performed. This is also referred to as “write-disturb.”
For flash memory, a whole block's data is erased and then programmed, such that a cell's total disturb time is equal to the time to program the entire block. Therefore, the disturb time is limited. However, for byte-erasable EEPROM, because each byte can be independently erased and programmed a large number of times, for example 10,000 times, the unselected cells' disturb time will accumulate. This accumulated disturb time may result in the unselected cells' data being changed.
It is therefore desirable to have a byte-erasable EEPROM that utilizes SONOS cells and that overcomes the problems of write-disturb.